This invention relates to providing high-speed video graphics through use of single ported memory chips on the video card.
High performance graphics processing commonly requires a specialized graphics frame buffer including a graphics engine in communication with a host processor over a bus. Control over a graphics frame buffer of this sort has been achieved by a variety of means, typically involving hardware configured to supervise the operation of the graphics engine. The graphics engine is typically controlled through commands from a host computer""s processor over a bus so as to provide request code and data from the host processor to the graphics engine. High-performance frame buffers in the prior art have three general characteristics.
First, the video board logic for performing texture processing, i.e. the integrated circuit that performs those functions, is separate from the circuitry for performing other frame buffer manipulations, such as graphics display requests. This results in limitations placed upon the performance of the graphics system due to the frame buffer designer""s having to arrange for a communication path between the texture processor and other components on the board.
Second, prior art video frame buffers arrange video memory in a linear fashion, such that consecutive memory locations represent the next pixel upon a given row of the display. In effect, prior art video memory arrangements track the scanline of the display.
Third, prior art video frame buffers store as one word in memory all information relevant to a particular display pixel. Consequently, acquiring the color value information for displaying a row of pixels upon the display requires skipping through video memory to obtain the values. This can be a very inefficient process.
Prior art video frame buffers, exemplified by the Edge III graphics processing system sold by Intergraph Corporation, and described in a technical white paper titled GLZ5 Hardware User""s Guide, which is incorporated herein by reference, represents the state of the prior art in graphics processing systems. However, the Edge III, as do other prior art video buffers, suffers from the three general limitations referenced above: lack of integration, linear video buffer memory, and consecutive placement of pixel information within the frame buffer. These limitations result in a graphics processing system that is not as efficient or speedy as it could be. The present invention resolves these issues.
The present invention, in accordance with a preferred embodiment, provides a device for storing pixel information for displaying a graphics image on a display. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. In this embodiment, the device has a video frame buffer memory having a series of consecutive addresses for storing information to be output to the display. The buffer memory is subdivided into a plurality of blocks, each block corresponding to a region of the display having a plurality of contiguous pixels. The device also has a processor for placing the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block. (Typically the processor is implemented by one or more resolvers.)
In a further embodiment, the frame buffer memory has a single port.
In a further embodiment, the placement of pixel information within the frame buffer includes a processor for placing at a second collection of consecutive addresses values for each of the pixels in the block associated with a first one of the plurality of additional planes.
In another embodiment, the present invention provides a device for storing pixel information for displaying a graphics image on a display, the information including an intensity value and a value associated with each of a plurality of additional planes for each pixel. This embodiment has a video frame buffer for storing information to be output to the display, the buffer memory having a plurality of banks, each bank being separately addressable and being subdivided into a plurality of blocks, each block corresponding to a region of the display having a plurality of contiguous pixels. This embodiment also has a processor for placing the pixel information within the frame buffer so that pixel information relating to first and second contiguous blocks is stored in different ones of the plurality of banks. In a further embodiment, the buffer memory has two banks, a first bank and a second bank, and the pixel information relating to first and second contiguous blocks is stored in the first and second banks respectively, so that there results a checkerboard form of allocation of pixels of the image over the display. In a further embodiment, the contiguous blocks are rectangular in shape, each block having more than 4 pixels on a side. In alternate embodiments, each block may have more than 7 pixels on a first side, and more than 7, 15, 31, 63, or 79 pixels on a second side.
In another embodiment, the invention provides a device for storing pixel information for displaying a graphics image on a display, the information including an intensity value and a value associated with each of a plurality of additional planes for each pixel. This embodiment has a video frame buffer memory having a series of consecutive addresses for storing information to be output to the display, the buffer memory subdivided into a plurality of banks, each bank being separately addressable and subdivided into a plurality of blocks, each block corresponding to a region of the display having a plurality of contiguous pixels; and a processor for placing the pixel information within the frame buffer so that, first, that pixel information relating to first and second contiguous blocks is stored in different ones of the plurality of banks, and second, in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.
In a further embodiment, the buffer memory has two banks, a first bank and a second, and the pixel information relating to first and second contiguous blocks is stored in the first and second banks respectively, so that there results a checkerboard form of allocation of pixels of the image over the display.
Related methods are also provided.